1. Field of the Invention
The present invention relates to a direct conversion receiver, and more particularly to improvement of a portable receiver such as a pager in which a direct conversion receiver is contained.
2. Description of the Related Art
In a receiver of a direct conversion reception system, a reception signal is mixed with a local oscillation signal in frequency to be converted into an intermediate frequency signal. The intermediate frequency signal is demodulated and is subjected to data processing. In this case, the difference between a desired reception signal and the local oscillation signal in frequency is derived as the intermediate frequency signal. For this purpose, it is necessary to control the local oscillation signal, and a PLL (phase locked loop) synthesizer is used for this control.
The PLL synthesizer has a function to compare between the local oscillation signal outputted from a VCO (voltage controlled oscillator) and the reference clock signal in frequency to control the VCO in accordance with the comparing result.
On the other hand, the receiver is provided with a control circuit for digital processing to take a timing with the desired wave signal, to process and display a data contained in the desired wave signal. A control system operation clock signal is used for the operation of this control circuit.
In this way, in the conventional direct conversion receiver which uses a PLL synthesizer, the reference clock signal for the PLL circuit and the control system operation clock signal for the control circuit are independent each other. Especially, in the pager, low cost, light weight and small size are required. However, at least two crystal oscillators are necessary for two clock signals. The crystal oscillator is an expensive part. Therefore, this is contrary to requirement of the low cost, the light weight and the small size.
Also, as to harmonic wave noise due to clock signals generated in the pager, there are two kinds of different noise components which are respectively generated from the clock signals of the two crystal oscillators. For this reason, it is very difficult to maintain radio reception characteristics.
Otherwise, a frequency synthesizer is described in Japanese Laid Open Patent Application (JP-A-Showa 58-81337). In the frequency synthesizer, each of a plurality of phase synchronizing circuits has a voltage controlled oscillator and the phase synchronizing circuits use a common reference oscillator. A switch sequentially selects one of the outputs from the voltage controlled oscillators. A variable frequency divider divides the output from the switch in frequency. A comparator compares the output from the variable frequency divider and the output of the reference oscillator in phase. A selector selects the output of the comparator in synchronous with the operation of the switch. A holding circuit holds the output of the selector as a control voltage to supply to the voltage controlled oscillator through a loop filter. The holding circuit is provided for every phase synchronizing circuit. A control section operates based on the output of the reference oscillator to control the switch, the variable frequency divider and the selector.
Also, a dual PLL apparatus is described in Japanese Laid Open Patent Application (JP-A-Heisei 3-60524). In a dual PLL apparatus, a first PLL circuit is provided with a common reference clock signal generator. A first phase frequency comparator is supplied with a reference clock signal from the reference clock signal generator. The output of the first phase frequency comparator is supplied to a first loop filter. The output of the first loop filter is supplied to a first voltage controlled oscillator. In a second PLL circuit, the reference clock signal is supplied to a delay circuit from the reference clock signal generator. The output of the delay circuit is supplied to a second phase frequency comparator. The output of the second phase frequency comparator is supplied to a second loop filter. The output of the second loop filter is supplied to a second voltage controlled oscillator. In this case, the output of the reference clock signal generator is supplied to the second phase frequency comparator of the second PLL circuit through the delay circuit. At the same time, the output of the reference clock signal generator is supplied to the first phase frequency comparator of the first PLL circuit directly without passing through the delay circuit.